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Increasingly fast edge-rates in today’s integrated circuits
cause detrimental high-speed effects, even in PCB
designs running at low operating frequencies. As driver ICs
switch faster, a growing number of boards suffer from signal
degradation, including over/undershoot, ringing,
glitching, crosstalk, and timing problems.
With HyperLynx software, we can plan routing constraints and PCB
stackup, set clock topologies,
simulate differential signals, and explore effective net
terminations prior to layout.
Equally valuable is the facility to verify a layout prior to producing costly
prototypes. Alternative routing or termination schemes can be tried and verified without incurring large material costs and significant project delays.
The HyperLynx suite of tools can be used in
virtually any design flow to help eliminate signal
integrity, crosstalk, and EMC problems early and eliminate the need for further board revisions.
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